DRAM and NAND: The Memory Supercycle Is Just Beginning, With No End in Sight
The memory industry spent thirty years teaching investors one lesson: never believe “this time is different.” Boom, over-invest, glut, collapse. Price the top early, because the top always comes. That instinct is now the most expensive mistake in semiconductors. The DRAM and NAND supercycle that began in 2024 is not late-cycle. It is early. And the mechanism that has ended every prior memory cycle has been disabled.
The demand is structural, not cyclical
Start with the numbers, because they are not subtle. IDC puts DRAM revenue at $418.6 billion in 2026, up roughly 177 percent year over year, with total memory rising from $226 billion in 2025 to $594.7 billion in 2026 and $790.4 billion in 2027. Bank of America frames the period as a supercycle on the scale of the 1990s boom, with DRAM revenue up 51 percent and NAND up 45 percent. Contract prices through early 2026 rose 90 to 95 percent quarter over quarter. DDR5 spot prices quadrupled from September 2025. Supplier inventories sit at two to four weeks.
The cyclical reflex is to see those figures and reach for the short. That reflex misreads what is buying the memory. This is not consumer content growth that saturates when handset and PC units roll over. It is a different, more expensive class of memory bought by hyperscalers who are price-insensitive and supply-anxious, securing allocation under multi-year contracts. The demand is structural because the thing driving it — AI training and inference infrastructure — is a multi-year capital program, not a product refresh. When the marginal buyer is building out compute at the scale of national infrastructure, the historical demand curve does not apply.
Supply physically cannot respond
The reason memory cycles ended was always the same: supply flooded in and broke price. That release valve is jammed.
High-bandwidth memory is the lever. A gigabyte of HBM consumes roughly four times the wafer area of standard DRAM, and it requires advanced packaging that cannot be conjured by flipping a switch on a commodity line. Every wafer reallocated to HBM is a wafer denied to everything else. AI is on track to absorb around 20 percent of global DRAM wafer capacity on an HBM-adjusted basis, against annual industry bit-supply growth constrained to 10 to 15 percent. The math does not close, and it does not close for years.
The three-player structure compounds it. Samsung, SK Hynix, and Micron now exercise pricing discipline that the fragmented industry of the 1990s never had, locking multi-year supply agreements with hyperscalers and selling out HBM capacity through 2026 and into 2027. Micron has moved to exit consumer memory entirely in favor of data-center customers. New greenfield fabs will not reach volume until late 2027 or 2028, and even then the output is pre-committed. Supply is not merely tight. It is structurally rationed by manufacturers who have learned that scarcity is more profitable than share.
Every new tier adds a new consumer of bits
Here is the argument the bears have not absorbed. This cycle is not one demand driver that will exhaust itself. It is a proliferation of new memory and storage tiers, each one a fresh consumer of bits stacked on top of the last. The cycle does not hand off from one runner to another. The runners keep multiplying while the first is still sprinting.
On the DRAM side, SOCAMM has pulled LPDDR — historically a phone and notebook part — into the data center as a new tier, offloading KV-cache from HBM to high-capacity low-power memory. NVIDIA’s Vera platform uses eight SOCAMM2 modules per CPU; AMD and Qualcomm are following. The tier is projected to represent 25 to 30 percent of AI inference memory by 2027, and it is already so demand-heavy that NVIDIA cut module capacity to manage an LPDDR shortage. CXL memory pooling has crossed into production, with Azure running the first commercial deployment and rack-scale pools addressing 100-plus terabytes for long-context inference. These are not refreshes of existing demand. They are new sockets that did not consume DRAM a year ago.
NAND is undergoing the identical transformation, and it is more consequential because NAND was the more brutally cyclical of the two. High-capacity QLC enterprise SSDs are displacing hard drives in the data center, migrating storage bits out of a different medium and into NAND, into the teeth of a concurrent HDD shortage. SanDisk’s 128-terabyte QLC platform is in qualification at multiple hyperscalers. The AI inference storage tier is additive on a scale the market has not priced: management estimates NVIDIA’s KV-cache architecture could drive 75 to 100 incremental exabytes of NAND demand in 2027, with a potential doubling in 2028. SK Hynix and NVIDIA are co-developing AI SSDs targeting 100 million IOPS by 2027.
Then there is the architecture that mirrors HBM on the flash side. High-Bandwidth Flash, standardized through a SanDisk and SK Hynix workstream at the Open Compute Project, creates an entirely new memory tier between HBM and SSD — NAND stacked like HBM, non-volatile, drop-in compatible with HBM4’s footprint, delivering 8 to 16 times the capacity at similar bandwidth and cost. Samples arrive in the second half of 2026, inference systems in 2027, with the market modeled from roughly $1 billion in 2027 to $12 billion by 2030. HBF is not a faster version of something that exists. It is a demand category that did not exist, with a date attached.
That is the engine of “no end in sight.” A generation bump migrates buyers from one SKU to another and adds bit supply. A new tier adds a new consumer. This cycle is making tiers.
The generation transitions do not end it
The instinctive bear catalyst is the next node or the next standard flooding the market. It does not apply here, because the relevant transitions are either too late or themselves supply-constraining.
DDR6 is a 2028-to-2030 event, well past the window in question, and it migrates rather than expands demand. 3D DRAM, the genuine escape from the planar scaling wall, is a 2030s technology with realistic mass production pointing to 2032 through 2035. NAND layer scaling and 3D DRAM are supply technologies, and when they arrive they add bits per wafer — which is the classic cycle-ender. But that is precisely the point: they are not here, and the transitions are so difficult that the migration period acts as a supply governor rather than a flood. Hard yield ramps and capital intensity put a floor under price during the changeover. The technology that would normally break the cycle is, for now, defending it.
The bear case, and why it is early
Intellectual honesty requires naming the way this ends. It ends if AI capital expenditure moderates at the same moment the greenfield capacity of 2028-2029 reaches volume — supply arriving into softening demand, the 1996 pattern restored. That scenario is real and worth tracking. The early texture is already visible in the divergence between AI contract prices ripping and consumer spot prices softening.
But that scenario requires two things to break together, and both are delayed. Capacity does not flood until late 2027 at the earliest, and the demand it would flood into is contracted years forward and expanding across new tiers faster than any single tier can saturate. A capex pause is the genuine risk, but it is a 2028 question being priced as a 2026 certainty. The market is still valuing these names as if a classic downturn is imminent, despite the strongest fundamental setup the industry has ever produced. That gap between fundamentals and valuation is the whole opportunity.
The repricing, not the peak
The cleanest way to hold this is to stop calling it a cycle. Memory is being repriced from a commodity into strategic AI infrastructure, and a repricing has no symmetric top the way a cycle does. The bits are going into more places, made by fewer suppliers, under longer contracts, constrained by a wafer-cannibalization dynamic that worsens with every HBM and HBF generation. The drivers stack instead of rotating. The supply cannot answer for years. And the technologies that would normally end it are either late or, in the transition, working in the cycle’s favor.
The supercycle is not in its final act. It is in its first.