CXL was sold as a capacity story: extend the memory pool past the DIMM slots soldered to the motherboard. Marvell’s argument with Structera is sharper than that. The pool itself is half-empty. The data sitting in DRAM is compressible, almost no CXL controller touches it, and Structera does — in dedicated silicon, at line rate, invisible to the host.

The number circulating is 3.64x, the top of the range Marvell cites for mixed real-world data types, which it claims match or closely approach what host-side LZ4 achieves in software. Field reporting has been more conservative; ServeTheHome quoted Marvell putting practical ratios at 1.8x to 2x. Both numbers point the same way. Even a flat 2:1 halves the effective cost per gigabyte of a memory pool, and memory is the single largest line item in that pool.